View AHA4501-050PQC_2426085.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ps4501-1100 2365 ne hopkins court pullman, wa 99163-5601 tel: 509.334.1000 fax: 509.334.9000 e-mail: sales@aha.com www.aha.com advanced hardware architectures product specification aha4501 astro 36 mbits/sec turbo product code encoder/decoder, 3.3v this product and the algorithm are covered under multiple patents pending.
advanced hardware architectures, inc. ps4501-1100 i table of contents 1.0 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 conventions, notations and definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 feedback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.5 data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6 synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6.1 encode synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.6.2 decode synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.6.3 resynchronize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.7 helical interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.8 data throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.9 encoding/decoding time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.10 summary of channel rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.11 latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.12 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.0 internal register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 configuration 0, address 0x00 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 configuration 1, address 0x01 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 configuration 2, address 0x02 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 feedback, address 0x03 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 quantization, address 0x04 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 corrections, address 0x05 - read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7 synchronization, address 0x05 - write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 status, address 0x06 - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9 control/interrupt, address 0x07 - read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10 reserved, address 0x08 - reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.0 performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.0 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1 system control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 input interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 output interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.0 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.0 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2.1 dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2.2 test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2.3 pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.0 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.0 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.0 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.1 available parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.2 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.0 related publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
advanced hardware architectures, inc. ii ps4501-1100 figures figure 1: functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 2: idata interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 3: input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4: 2d interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5: encoded/interleaved data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6: encoding at the maximum input rate (bit/clock) with maximum output rate (bit/clock). . . . . . . . . . . . . . . 7 figure 7: encoding at less than maximum input rate with maximum output rate . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 8: decoding with continuous input data rate - stiter not asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 9: decoding with burst input data rate - stiter not asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 10: decoding with burst input data rate - stiter asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 11: dump feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 12: turbo product code vs. reed-solomon/viterbi performance comparison . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13: comparison of tpc code types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 14: performance curve of e b /n o for ber of 10 -5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 15: pinout ? 100 mqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 16: current vs. data rate (typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 17: signal timing vs. output load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 18: data input timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 19: data output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 20: microprocessor interface timing (write); procmode=0, muxmode=0 . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 21: microprocessor interface timing (read); procmode=0, muxmode=0 . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 22: microprocessor interface timing (write); procmode=0, muxmode=1 . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 23: microprocessor interface timing (read); procmode=0, muxmode=1 . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 24: microprocessor interface timing (write); procmode=1, muxmode=0 . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 25: microprocessor interface timing (read); procmode=1, muxmode=0 . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 26: interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 27: clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 28: power on reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 29: aha4501 package specifications ? 100 mqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
advanced hardware architectures, inc. ps4501-1100 iii tables table 1: recommended qshift values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 2: channel rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3: register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4: supported codes with recommended feedback values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5: pin designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6: data input timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 7: data output timing requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8: microprocessor interface timing requirements - write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 9: microprocessor interface timing requirements - read; procmode=0, muxmode=0 . . . . . . . . . . . . 28 table 10: microprocessor interface timing requirements - write; procmode=0, muxmode=1. . . . . . . . . . . . . 29 table 11: microprocessor interface timing requirements - read; procmode=0, muxmode=1 . . . . . . . . . . . . 30 table 12: microprocessor interface timing requirements - write; procmode=1, muxmode=0. . . . . . . . . . . . . 31 table 13: microprocessor interface timing requirements - read; procmode=1, muxmode=0 . . . . . . . . . . . . 32 table 14: interrupt timing requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 15: clock timing requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 16: power on reset timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 17: pqfp (plastic quad flat pack) 14 20 mm package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ps4501-1100 page 1 of 36 advanced hardware architectures, inc. 1.0 introduction the aha4501 is the first single-chip forward error correction lsi device using turbo product codes (tpc). the device operates as a block code encoder at the input or a block code decoder at the output of a communication channel. the device supports various programmable features, such as block size, codes and code rates, to optimize various communication channel needs for error performance and data throughput. turbo product codes offer a higher performance alternative to reed-solomon or reed-solomon concatenated with viterbi error correction methods. when encoding, the device appends the error correction code (ecc) bits to the blocks, and outputs the encoded blocks. when decoding, the device accepts soft decision values and stores the data as a block in its internal ram. the block is then decoded iteratively by running it through the device?s soft in/soft out (siso) decoder. the device iterates to the maximum programmed iteration limit. the decoded block is then output through the device output data port. this specification describes the functional operation, programming, timing and ordering information. please contact aha for additional support material, including evaluation software and relevant technical publications; or visit our website at http://www.aha.com. 1.1 conventions, notations and definitions ? code block ? a data stream to be encoded or decoded is segmented into blocks for processing by the aha4501. data in a code block is configured as a 2d or 3d array. ? axis iteration ? decoding one axis of an array (all x rows, all y columns, or all z columns). ? full iteration ? decoding all axes of an array (all rows and columns). ? soft value ? input to the decoder from either an analog/digital converter(adc) or digital demodulator. ? code rate ? ratio of the number of data bits to the number of data and ecc bits. ? data rate ? the rate at which unencoded data is input to the device when encoding or output from the device when decoding. ? channel rate ? the rate at which encoded data is output from the device when encoding or input to the device when decoding. note that system channel rate may be different due to external synchronization marks or other overhead. ? original array (oa) ? the soft decision input data array. data is stored as a 6 bit soft value per location to support the maximum 6 bit input quantization. ? intermediate storage array (isa) ? the storage array for data between iterating. ? hard decision array (hda) ? the hard decision output. data is stored as one bit per location. ?(n 1 ,k 1 )x(n 2 ,k 2 ) ? a general representation of a 2d block code for use in the descriptions to follow in this specification. for example, in a (64,57)x(64,57) code; n 1, n 2 =64 represents the length of the data + ecc bits, and k 1 ,k 2 =57 represents the length of only the data bits. 3d codes are represented as (n 1 ,k 1 )x(n 2 ,k 2 )x(n 3 ,k 3 ) ? vector ? one row or column of data in a block. ? latency ? the time from the first bit of a block in to first bit of the same block out. ? active low signals have an ?n? appended to the end of the signal name. for example, mcsn and resetn. ? hex values are represented with a prefix of ?0x?, such as register ?0x00?. binary values do not contain a prefix. 1.2 features performance: maximum 50 mbits/sec channel rate encoding 36.5 mbits/sec channel rate decoding for a 64x57 square code at two iterations two or more devices can be used in parallel to increase throughput optional ?helical? interleaving (encoding) and deinterleaving (decoding) flexibility: internal buffering allows continuous data streaming programmable block size from 256 to 4096 bits two or three dimensional blocks programmable number of iterations per block up to 32 programmable quantization up to 6-bits for soft or hard decision input data (decoding) support for external synchronization system interface: serial or 8-bit parallel input and output data ports selectable microprocessor interface for intel or motorola processors control commands for: decode, encode, soft reset, resynchronize and dump current block system interrupts include block decode complete, block correction incomplete, sync mark mismatch number of corrections per block accumulated in an internal register others: 3.3 volt operation 100 pin quad flat package output signals may be tristated to facilitate board level testing
page 2 of 36 ps4501-1100 advanced hardware architectures, inc. figure 1: functional block diagram 2.0 functional overview the sections below describe the various configurations, programming and other special considerations for developing an error correction system using the aha4501. refer to figure 1 : functional block diagram for the data flow while reading the remainder of this section. 2.1 data input data is input to the idata port via a fully synchronous ready/accept handshake. data is registered internally on the rising edge of clock when both the ready input (irdy) and the accept output (iacpt) are asserted. refer to section 8.0 figure 18 for data input timing details. when encoding, data is input either serially (one bit per handshake) on idata[0], or in parallel (one byte per handshake) on idata[7:0]. when parallel loading is used, iacpt toggles at most once every eight clocks since the data is serialized internally. when decoding, data is input one quantization value per handshake on idata[(q-1):0] where q is the input quantization size. the quantization size is configurable based on the setting of qsize[1:0] within the quant register. the qmode[1:0] bits within the quant register determine the type of input data. the input data may be 2 ? s complement, sign/magnitude, or unsigned. when qmode = ? 00 ? , all unused idata inputs should be tied to idata[q-1]. when qmode = ? 01 ? or ? 10 ? , all unused idata inputs should be tied to ground. figure 2 shows example connections when qsize = ? 01 ? (3 bits). idata[7:0] siso input isa output odata[7:0] ordy oacpt osync encoder/ hda sram feedback multiplier oa sram control registers sram microprocessor interface muxmode mdata[7:0] procmode mcsn ma[2:0] mrdn_dsn mwrn_rwn male mintn_intr irdy iacpt isync clock clock resetn aha4501 decoder mrdy_dtackn
ps4501-1100 page 3 of 36 advanced hardware architectures, inc. figure 2: idata interface the value of qshift[1:0] in the quant register sets the number of bit positions the input data is shifted left internally before decoding begins. the idata bits should be shifted to fill the internal resolution, allowing for higher precision for internal processing. the increased precision results in the best possible decoding performance. throughput and latency are not affected by the quantization size or shift values. the following equations should be used to determine how to set qshift[1:0] in relation to qsize[1:0]. in each equation, qsize and qshift are the values represented by the programmed value, instead of the programmed value itself. for example, if qsize[1:0] = ? 01 ? , qsize in the following equations would be 3 bits. qmode[1:0] = ? 01 ? or ? 10 ? : qsize + qshift < 6 or qshift < 6 - qsize qmode[1:0] = ? 00 ? : qsize + qshift < 7 or qshift < 7 - qsize for best performance, do not shift the data beyond the internal resolution (7 bits). the above equations guarantee that this does not occur. for example, if a particular system has three quantization bits using qmode[1:0] = ? 00 ? , the following shows the values to program for each register. qsize[1:0] = ? 01 ? (3 bit input values) qshift < 7 - qsize qshift < 7 - 3 qshift < 4 qshift[1:0] = ? 11 ? (shift left of 3) for best performance, do not shift the data beyond the internal resolution (7 bits). the above equations guarantee that this does not occur. the following table shows recommended qshift values for each qmode and qsize. table 1: recommended qshift values for qmode = ?00? connect idata as shown for qmode = ?01? or ?10? connect idata as shown idata7 idata2 idata6 idata3 idata4 idata5 idata2 idata1 idata0 idata1 idata0 aha4501 idata7 idata2 idata6 idata3 idata4 idata5 idata2 idata1 idata0 idata1 idata0 aha4501 qsize (bits) 2s complement sign/magnitude unsigned 1na3na 2333 3322 4211 5100 6 0 na na
page 4 of 36 ps4501-1100 advanced hardware architectures, inc. 2.2 encoding when encoding a 2d block for a (n 1 ,k 1 )x(n 2 ,k 2 ) code, k 1 k 2 data bits constitute one block. when encoding a 3d block for a (n 1 ,k 1 )x(n 2 ,k 2 )x(n 3 ,k 3 ) code, k 1 k 2 k 3 data bits constitute one block. the input data is loaded into the oa sram input buffer as an array with 1 bit per sram location. encoding begins once the entire block is in the oa sram buffer. the device ? s oa sram can accommodate another block while the device encodes the first block in the buffer. ecc bits are generated for each x-axis row of the block array and are appended to the end of the vector. each y-axis column and each z- axis column (if applicable) are then encoded in the same fashion. the encoded block is loaded into the hda sram output buffer and then transferred out of the device through the odata port. the following figure shows one block of a (8,4)x(8,4) product code. ? d ? represents data and ? e ? represents ecc bits. organizing data blocks into arrays and interleaving are performed by the device automatically without any system intervention. ddddeeee ddddeeee ddddeeee ddddeeee eeeeeeee eeeeeeee eeeeeeee eeeeeeee the following list of register settings shows an example program to encode data. in this example, the outgoing data is not interleaved, the incoming data loads in parallel on the idata[7:0] bus, the block code is a 2d (64,57)x(64,57) product code, and the output asserts osync with the first bit of every third block. osync usage is discussed further in section 2.6. -program config0 register inter 0 pa r_ s er 1 -program config1 register xcode[2:0] 111 reserved bits 00011 -program config2 register ycode[2:0] 111 zcode[2:0] 000 -program sync register sync mark frequency[3:0] 0011 -program control register encode 1 after these registers are programmed, the aha4501 asserts iacpt to allow iacpt-irdy handshakes. 2.3 decoding decoding is done in an iterative fashion. decoding begins once a complete received data block is available in the oa sram. the device ? s oa sram can accommodate another block while the device decodes the first block. each full iteration begins by passing an x-row from the oa sram into the soft input soft output (siso) decoder. the siso output is multiplied by a programmable xfeedback[2:0] value, and stored in the isa sram. the completion of all x-rows constitutes one axis iteration. refer to section 2.4 for an explanation of the feedback multipliers. next, each y-axis column from the oa sram is passed into the siso decoder. the siso output is multiplied by the programmable yfeedback[2:0] value and stored in the isa sram. the completion of all y-columns constitutes one axis iteration. if a 3d code is being decoded, each z-axis column from the isa sram is passed into the siso decoder. the siso output is multiplied by the programmable zfeedback[2:0] value and stored in the isa sram. the completion of all z-columns constitutes one axis iteration. one full iteration is completed when one x and one y axis iteration is complete for a 2d code; or one x, one y, and one z axis iteration is complete for a 3d code. the iterations continue until the iteration counter equals the number programmed in iter[4:0] within the config0 register. the following sequence may be used to program the aha4501 for decoding data. this configuration decodes the same blocks of data encoded using the configuration shown in the encoding section. - program config0 register pa r_ s er 1 when decoding, the par_ser bit configures the output on odata[7:0]. in this case, parallel output is selected. stiter 1 the stiter bit causes the aha4501 to stop decoding when a full iteration completes with no corrections. iter[4:0] 00100 set for 4 iterations. refer to section 4.0 performance curves . - program config1 register xcode[2:0] 111 (64,57) code type reserved bits 00011
ps4501-1100 page 5 of 36 advanced hardware architectures, inc. -program config2 register oecc 0 no ecc bits will be output with the data. xfbck[2] 1 usually set for a feedback multiplier of 1/2 with square codes. ycode[2:0] 111 (64,57) code type -program feedback register yfeedback[2:0] 100 -program quant register qmode[1:0] 01 this depends on the type of adc selected to recover the transmitted data. for this example sign/magnitude is selected. qsize[1:0] 10 this also depends on the type of adc selected. for this example, 4 bit quantization is selected. qshift[1:0] 01 this should be set for a 1 bit left shift for the best possible internal precision with 7 bit internal resolution and 4 bit quantization. refer to section 2.1 data input for guidelines on setting qshift[1:0]. -program sync register sync mark length[3:0] 0101 the length of the sync mark is selected by the system designer. for this example, the sync mark length is 20 bits long. sync mark frequency[3:0] 0011 -program control register decode 1 after these registers are programmed, the aha4501 asserts iacpt and discards the input data until isync is asserted. 2.4 feedback the tpc algorithm uses feedback, or weighting, values for performance timing. after each axis iteration, the output of the siso decoder is multiplied by the feedback constant for that axis. these values are then fed back into the siso for future iterations. the feedback multiplier values used for each code axis vary from 1/4 to 11/16 depending on the number of iterations and system parameters (soft input bits, resolution). the feedback multipliers must be tuned to give optimum decoder performance in a given system. the following describes the tuning process. the choice of feedback multiplier has no effect on throughput or latency. for 2d square (xcode[2:0] = ycode[2:0]) codes, a typical feedback multiplier value for both axes at 3 or 4 iterations is 8/16. for 3d cubic (xcode[2:0] = ycode[2:0] = zcode[2:0]) codes, a typical feedback multiplier value at 6 iterations is 7/16. when using non-square or cubic codes, the following general rules should be applied. parity codes should have their feedback multiplier values set higher than hamming codes when mixed. for example, in a (32,26)x(32,26)x(4,3) code, the x and y feedback multipliers should be set to 6/16 while the z feedback should be set to 9/16 or 10/16. when mixing hamming codes with shorter hamming codes, the feedback multiplier should be set slightly higher for the shorter code. for example, in a (64,57)x(32,26) code, the x feedback multiplier could be set to 8/16, while the y feedback multiplier could be set to 9/16. the feedback values must be tuned for the number of iterations allowed in a system. for less iterations than the above guidelines, the feedback values should be increased. for more iterations, the values should be decreased. for example, when using a (64,57)x(64,57) code with only 2 iterations, the feedback multiplier for both axes should be set to 10/16. conversely, in a system that allows 12 or more iterations, the value for the feedback should be set to 7/16. the feedback may also need to be tuned depending on the number of soft input bits (qsize[1:0]). this parameter will only affect the optimum feedback multiplier value slightly, meaning that it should be adjusted by only 1/16 or 2/ 16 to allow for these differences. since systems vary widely, the system designer should experiment with various feedback multiplier values to obtain the best performance. recommended starting values for feedback are listed in table 4. 2.5 data output data is output through the odata port via a fully synchronous ready/accept handshake. data is transferred on the rising edge of clock when both the accept input (oacpt) and the ready output (ordy) are asserted. refer to section 8.0 figure 19 for data output timing details. when encoding, data is always output serially on odata[0]. when decoding, data can be output either serially on odata[0] or in 8-bit parallel on odata[7:0]. 2.6 synchronization since the tpc is a block code, data synchronization is required to correctly decode each block. external synchronization circuitry is required to insert and detect synchronization marks. the aha4501 provides features to remove the synchronization marks and indicate correct synchronization mark placement.
page 6 of 36 ps4501-1100 advanced hardware architectures, inc. the isync and osync signals are handled in the same fashion as idata[7:0] and odata[7:0]. isync is registered internally on the rising edge of clock when both irdy and iacpt are asserted. osync is only valid when the ordy output signal is asserted. 2.6.1 encode synchronization when encoding, the aha4501 provides the output signal osync to indicate when a synchronization mark should be inserted in the data stream. osync is asserted with the first data bit of each x output blocks, where x is the value of sync mark frequency[3:0] programmed within the sync register. the system can then use osync to insert a synchronization mark in the encoded data stream before transmitting. 2.6.2 decode synchronization when decoding, the synchronization circuitry depends on the channel and demodulation method. for the first block after reset, the aha4501 discards the input data on idata[7:0] until the isync signal is asserted. the first bit of the block is registered on the same clock as isync is asserted. after the first block, synchronization marks are automatically removed from the data by programming sync mark length[3:0] and sync mark freq[3:0] within the sync register. sync mark length[3:0] configures the aha4501 to remove x bits from the start of every synchronization block, where x is 4 times sync mark length[3:0]. the aha4501 expects a synchronization mark at the block interval specified by sync mark frequency[3:0]. if isync is not asserted with the first bit after sync mark length[3:0] handshakes, a loss of synchronization is indicated by assertion of the smmis bit in the interrupt register. if the system designer chooses not to use the synchronization support logic of the aha4501, the isync signal must be tied high. the corrections[9:0] count and corinc bit can also be used to indicate a loss of synchronization. the control microprocessor may use this information to send a resynchronize command to cause the aha4501 to synchronize on the start of the next data block by discarding input data until isync is asserted. the osync signal is asserted with the first bit of every block when decoding. 2.6.3 resynchronize loss in synchronization may be detected using smmis, corinc, niter[4:0], and corrections[9:0]. the control microprocessor may use this information to determine that the aha4501 is not synchronized and issue a resynchronize command. the aha4501 does not automatically resynchronize the data stream unless instructed to do so by the microprocessor. the resynchronize command causes the aha4501 to stop decoding blocks and discard the input data until isync is asserted. the aha4501 continues to output any blocks that have been decoded and are waiting to be unloaded from the hda sram. the aha4501 registers the input from idata[7:0] on the same clock as isync is asserted. 2.7 helical interleaving the device can optionally interleave when encoding and deinterleave when decoding. interleaving data spreads bursts of noise across all axes of the block code for the best error correction performance in burst channel use. interleaving in the aha4501 is applied after encoding takes place. deinterleaving in the aha4501 takes place before the decoding operation. helical interleaving is applied along a diagonal path through the encoded block. data is output along diagonal lines from the upper left to lower right corner (for a 2d code). the first diagonal output starts with the bit row 1, column 1 followed by the diagonal starting at row 1, column 2. for 3d codes, instead of reading diagonally through the 2d array, interleaving reads diagonally through a cube of data. the example below shows how interleaving is applied for a 2d (64,57)x(64,57) code. figure 3: input block note: the number reflects the bit order, including generated ecc bits. 0123 63 64 65 66 67 127 128 129 191 192 193 4032 4033 4095 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 . . . . . . . . .
ps4501-1100 page 7 of 36 advanced hardware architectures, inc. the encoded, interleaved data output is taken along diagonal lines starting with bit 0 as shown below. the order of the interleaving is noted for each diagonal line. figure 4: 2d interleaving for the (64,57)x(64,57) block, the data output from the aha4501 is: 0, 65, 130, ..., 4095, 1, 66, ..., 4031, 4032, 2, 67, ..., ..., 63, 64, ..., 4094 for a total of 4096 bits output. the aha4501 operating as a decoder deinterleaves the block to restore it to its orginal order. figure 5: encoded/interleaved data output data bits are output from the encoder in row order from left to right. 3d interleaving/ deinterleaving is done by reading/writing cells diagonally through the x, y, and z dimensions. note that the data rate drops when interleaving and/or deinterleaving as discussed in section 2.8. 2.8 data throughput the aha4501 contains internal buffering at the input (oa sram) and the output (hda sram) to allow the device to maintain a constant input data rate with no external memory. the aha4501 is capable of loading a code block into 1/2 of the oa sram while it is processing a second code block from the other 1/2 of the oa sram. the second code block is loaded into the 1/2 of the hda sram while a third code block can be output from the other 1/2 of the hda sram. this ping-pong buffer arrangement on the input and output sides of the aha4501 allows code blocks to be processed in a continuous stream as long as the overall bandwidth of the device is not exceeded. when encoding a data block, the data can be transferred continuously at up to one bit per clock, independent of the code type. a 1 clock delay occurs between blocks. when decoding a code block and not deinterleaving, the maximum input rate is one soft value per clock, independent of code type. a 1 clock delay occurs between blocks. when decoding a code block and deinterleaving, the maximum input rate is one soft value every 3 clocks, independent of code type. a 1 clock delay also occurs between blocks when deinterleaving. the following diagrams illustrate how code blocks are processed through the aha4501 and when the internal status registers update the status of the blocks. in figure 6, the data is input at a bit per clock and encoded. the data is encoded by appending ecc bits to the data. note that the data is always encoded faster than data can be input to the device. since the output is operating at a bit/clock and there are more output bits than input bits, the output is the limiting factor in the system. after the initial buffer loading, the input must wait for the output to finish unloading a block before accepting another block. the ratio of the input block size to the output block size is the code rate . figure 6: encoding at the maximum input rate (bit/clock) with maximum output rate (bit/clock) 0123 63 64 65 66 67 127 128 129 1 191 192 193 4032 4033 4095 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 . . . . . . . . . 2 4 126 127 3 0 65 130 . . . 4095 1 66 131 . . . 4032 2 67 4033 368 63 64 4094 4030 4029 . . . 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 4031 . . . 3968 1 input data encoding output data compl interrupt 234 5 1 2 3 1 2 3 4 1 2 3 4
page 8 of 36 ps4501-1100 advanced hardware architectures, inc. in figure 7, the data is input at a slower rate than the output rate which allows a constant input data rate . in figure 8, the received data is input at a bit every other clock and decoded. when decoding, the decode time is variable depending on the number of iterations used, type of code and the status of the stiter bit. in this example, the iterations are set so that the decode time is approximately equal to the data input time. for continuous data input, set the iter[4:0] count such that the decoder time is less than the data block input time. refer to section 2.9 encoding/decoding time for decoding time calculations . in figure 9, the received data is input at a bit every other clock and decoded. when decoding, the decode time is variable depending on the number of iterations used, type of code and the status of the stiter bit. in this example, the iteration count in iter is set to 6 to illustrate a case where the decode time is the limiting factor in the throughput. to achieve maximum decoder performance with burst data, set the iteration count such that the decoder time is equal to or exceeds the data block input time. figure 7: encoding at less than maximum input rate with maximum output rate figure 8: decoding with continuous input data rate - stiter not asserted figure 9: decoding with burst input data rate - stiter not asserted input data encoding output data compl interrupt 1 2 3 4 1 2 3 1 2 3 4 1 2 3 4 input data decoding output data status/corrections register block 1 block 2 1 2 3 block 3 1 2 3 1 2 3 corinc & compl interrupt 1 2 3 input data decoding output data status/corrections register block 1 block 2 block 4 1 2 3 4 1 2 3 4 block 3 5 1 2 3 corinc & compl interrupt 1 2 3 4
ps4501-1100 page 9 of 36 advanced hardware architectures, inc. in figure 10, the received data is input at a bit per clock and decoded. in this example, the iteration count in iter is set to 6 and the stiter bit is set to illustrate a case where the decode time is variable depending on the number of iterations required to correct the errors in the code block. in this example, blocks 1, 2, 4, and 5 decode in 2 iterations while block 3 requires 6 iterations to decode. when decoding, writing a one to the dump bit within the control register causes the module to stop iterations on the current block and send it to the output data port. the dump occurs upon completion of the axis iteration following the current axis iteration. the worst case delay is two axis iterations (which is equal to one full iteration for 2-d codes). decoding then begins on the next (already loaded) data block, and another block can begin loading. in figure 11, the example from figure 10 is shown to illustrate the dump feature. in the third decoding block, dump is set in the fourth iteration. the decoder finishes the current full iteration before it outputs the block. decoding on block 4 starts normally. the dump feature is useful when using an input buffer with the stiter configuration bit, and the input buffer becomes full. note that the dump bit does not cause loss of data. upon completion of the dump, the compl interrupt bit is set, and the corinc bit is set if any corrections were made in the last axis iteration. this bit should not be set when encoding . figure 10: decoding with burst input data rate - stiter asserted figure 11: dump feature input data decoding output data status/corrections register block 1 block 2 block 4 1 2 3 4 1 2 3 block 3 5 1 2 4 5 6 4 block 5 corinc & compl interrupt 1 2 3 4 3 5 5 input data decoding output data status/corrections register block 1 block 2 block 4 1 2 3 4 1 block 3 5 1 2 6 4 block 5 corinc & compl interrupt 1 2 3 4 3 5 5 12 3 2 12 1234 12 4 5 12 iterations dump bit set
page 10 of 36 ps4501-1100 advanced hardware architectures, inc. 2.9 encoding/decoding time the time required to encode a data block is equivalent to the time to decode 1 code block with 1 full iteration. since the aha4501 can perform 1 full iteration faster than data can be transferred serially through the encoded data output port, the output rate is the limiting factor for the overall data rate. the time to decode a code block depends on the input clock frequency, the code type, and the number of iterations. the following equations are used to compute the overall decoding time. the decoding time can be used to compute the data rate and latency. note that if the stiter bit is set in the config0 register, the aha4501 stops iterating when there are no corrections. when the stiter bit is set, the number of iterations is unpredictable and the decode time may be shortened or lengthened depending on the error content data stream. the number of iterations will never be more than the number set in iter[4:0] even when stiter is set. nx = length of entire vector (data + ecc) for x axis code kx = length of data vector for x axis code ny = length of vector (data + ecc) for y axis code ky = length of data vector for y axis code nz = length of vector (data + ecc) for z axis code (nz=1 for 2d codes) kz = length of data vector for z axis code (kz=1 for 2d codes) i = iterations d = number of clocks to decode one block f = clock frequency (hz) r ch = channel rate (bits/sec) r d = data rate (bits/sec) c 1 ,c 0 = decode constants, see table 1. cr = code rate. code rate for a (nx,kx) x (ny,ky) x (nz,kz) code: clocks to decode an entire block: d = c 1 x i + c 0 maximum channel rate for a 3d block (for a 2d block, nz = 1): maximum data rate for a 3d block (for a 2d block, kz=1): if interleaving is used, the maximum channel rate will be the lesser of r ch listed above and f / 3 and the maximum data rate will be the lesser of r d listed above and ( f x cr)/ 3 . cr kx ky kz nx ny nz ----------------------------- - ?? ?? = r ch nx ny nz f d ------------------------------------- - = r d kx ky kz f d ------------------------------------ - =
ps4501-1100 page 11 of 36 advanced hardware architectures, inc. 2.10 summary of channel rates the channel rates listed in the following table are calculated with a 50 mhz clock frequency. the channel rate changes in proportion with the change in clock frequency. for example, if the clock frequency is 25 mhz, all channel rates are divided by 2. to compute data rate, multiply these values by the overall code rate. note: this table does not include all codes supported by the device. for decode times and code rates for codes other than those listed here, see the aha4501 windows evaluation software. table 2: channel rates block configuration (n 1 ,k 1 )x(n 2 ,k 2 )x(n 3 ,k 3 ) number of iterations 23 6 c 1 c 0 (64,57)x(64,57) decode time (clocks) 5612 7963 15016 2351 910 code rate = .793 channel rate (mbits/sec) 36.5 25.7 13.6 (32,26)x(32,26)x(4,3) decode time (clocks) 8368 11917 22564 3549 1270 code rate = .495 channel rate (mbits/sec) 24.5 17.2 9.1 (16,11)x(16,11)x(16,11) decode time (clocks) 7816 11197 21340 3381 1054 code rate = .325 channel rate (mbits/sec) 26.2 18.3 9.6 (32,26)x(16,11)x(8,4) decode time (clocks) 7992 11421 21708 3429 1134 code rate = .278 channel rate (mbits/sec) 25.6 17.9 9.4 (64,57)x(32,26) decode time (clocks) 2972 4227 7992 1255 462 code rate = .724 channel rate (mbits/sec) 34.5 24.2 12.8 (32,26)x(16,11)x(4,3) decode time (clocks) 4304 6141 11652 1837 630 code rate = .419 channel rate (mbits/sec) 23.8 16.7 8.8 (64,57)x(8,4)x(4,3) decode time (clocks) 4448 6357 12084 1909 630 code rate = .334 channel rate (mbits/sec) 23.0 16.1 8.5 (32,26)x(32,26) decode time (clocks) 1540 2211 4224 671 198 code rate = .660 channel rate (mbits/sec) 33.2 23.2 12.1 (16,11)x(16,11)x(4,3) decode time (clocks) 2224 3181 6052 957 310 code rate = .354 channel rate (mbits/sec) 23.0 16.1 8.5 (32,26)x(16,11) decode time (clocks) 860 1239 2376 379 102 code rate = .559 channel rate (mbits/sec) 29.8 20.7 10.8 (16,11)x(16,11) decode time (clocks) 464 679 1324 215 34 code rate = .473 channel rate (mbits/sec) 27.6 18.9 9.7
page 12 of 36 ps4501-1100 advanced hardware architectures, inc. 2.11 latency since product codes are block codes, the data for an entire block must be input to the aha4501 before encoding or decoding can start. if interleaving is not enabled, the latency (in clock cycles) from the first input bit of a block to the first output bit of the same block is: if interleaving is enabled the latency for encoding a block (in clock cycles) is: block input time + block encode time + 17 the latency for decoding an interleaved block (in clock cycles) is: block input time + block decode time + 19 for example, the block decode time and latency to decode a (64,57)x(64,57) non-interleaved code with 2 iterations and a 50 mhz clock are shown below. the example assumes the input and output operate at maximum speed. the time to decode a (64,57)x(64,57) block (as shown in section 2.10) is: assuming that the data is input at the decode data rate (i.e., the block input time equals the block decode time) the total latency is: 2.12 microprocessor interface the aha4501 is capable of interfacing directly to a microprocessor for embedded applications. all register accesses to the aha4501 are performed on an 8-bit bidirectional bus, using either an intel ? or motorola ? style interface. the interface is in motorola ? mode when the procmode input signal is asserted, otherwise the interface is in intel ? mode. a muxmode input is also provided to allow the data and address to be multiplexed on the mdata[7:0] bus. the data and address are multiplexed when muxmode is asserted, otherwise both mdata and ma busses are used. refer to section 8.0 for microprocessor interface timing diagrams. 3.0 internal register programming table 3: register summary notes: 1) u - these bits remain unchanged after a soft reset. 2) the reserved bits in register address 0x01 must be written to 00011 after any hard reset. address r/w mnemonic register name hard reset soft reset 0x00 r/w config0 configuration0 0x26 unchanged 0x01 r/w config1 configuration1 0xe0 unchanged 0x02 r/w config2 configuration2 0x38 unchanged 0x03 r/w feedback feedback 0x24 unchanged 0x04 r/w quant quantization 0x0c unchanged 0x05 r correct corrections/ 0x00 unchanged w sync synchronization 0x06 r status status 0x00 unchanged 0x07 r interrupt interrupt 0x00 uuuuu000 w control control 0x08 reserved reserved 0x0c unchanged block input time block decode(encode) time + 9 + 5612 1 50 mhz ------------------- ?? ?? 112.2 s = 2112.2 s 9 1 50 mhz ------------------ ?? ?? + 224.47 s =
ps4501-1100 page 13 of 36 advanced hardware architectures, inc. 3.1 configuration 0, address 0x00 - read/write this register is initialized to 0x26 after hard reset, unchanged after soft reset. inter - deinterleave incoming data when decoding, and interleave outgoing data when encoding. see section 2.1 data input for details about interleaving/deinterleaving. par_ser - parallel/serial mode select.when par_ser is set during encoding, the device will input 8 bits in parallel from the idata[7:0] bus. the first encoded bit output on odata[0] will be from idata[0]. in other words, idata[0] is the lsb and idata[7] is the msb. the irdy pin controls the flow of data into idata[7:0]. typically, the iacpt pin will be active 1 out of 8 clock cycles when in parallel mode. during encoding the output is always bit serial on odata[0]. when par_ser is not set during encoding, the data is input from idata[0] one bit per handshake and output from odata[0] one bit per handshake. the unused pins idata[7:1] should not be left floating, they should be tied to gnd. when par_ser is set during decoding, the device will pack the output decoded data bits into 8-bit bytes on odata[7:0]. the output bit on odata[0] is generated from the first soft input symbol. odata[0] is the lsb and odata[7] is the msb. the ordy pin controls the flow of data out of odata[7:0]. typically, the ordy pin is active 1 out of 8 clock cycles when in parallel mode. the input data will be on idata[n-1:0] where n is the number of soft input bits. the unused idata pins should not be left floating, they should be tied to gnd. when par_ser is not set during decoding, the data is input from idata[n-1:0] one soft symbol per handshake where n is the number of soft input bits. the decoded data is output from odata[0] one bit per handshake. stiter - stop iterating when no corrections. used only when decoding; the aha4501 can determine if future iterations can be useful. when this bit is set, the module stops iterating when the decoding is completed. when cleared, it always executes the number of full iterations in iter[4:0]. note that in either case, the number of full iterations does not exceed iter[4:0]. at any time after the first iteration, the microprocessor can also write a 1 to the dump bit in the control register, in which case all future iterations are cancelled and the current block is output. this bit is ignored when encoding. iter[4:0] - maximum iterations. used only when decoding; number of full iterations to perform for each block. one full iteration is defined as decoding the x and y axes for a 2d block or all x, y and z axes for a 3d block. the value of 0x0 indicates 32 full iterations. if stiter is asserted, less iterations than the iter[4:0] count may be performed. this value is ignored when encoding. 3.2 configuration 1, address 0x01 - read/write this register is initialized to 0xe0 after hard reset, unchanged after soft reset. xcode[2:0] -code for x axis of product array. see config2 register zcode [2:0] description. res - reserved bits [4:0]. must be written to 00011. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x00 inter par_ser stiter iter[4:0] address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x01 xcode[2:0] res
page 14 of 36 ps4501-1100 advanced hardware architectures, inc. 3.3 configuration 2, address 0x02 - read/write this register is initialized to 0x38 after hard reset, unchanged after soft reset. oecc - output ecc bits. used only when decoding. when cleared, only the data bits are output; total output bits per block = k 1 k 2 (2d), or k 1 k 2 k 3 (3d). when set, both the data and ecc bits are output; total output bits per block = n 1 n 2 (2d), n 1 n 2 n 3 (3d). xfbck[2] -x axis feedback bit 2. see description for feedback register (0x03). ycode[2:0] -code for y axis of product array. see zcode[2:0] description for code definitions. zcode[2:0] -code for z axis of product array. set to 000 for all 2d codes. each code axis is defined as follows: the following rules must be followed when selecting codes: 1) the (4,3) parity code and ? n 0 code ? is illegal for both the x axis code and the y axis code. 2) 2d codes require that the x dimension product code and the y dimension product code be at least 16 bits. 3) n 1 x n 2 x n 3 must be less than or equal to 4096. the aha4501 is designed to allow any combination of x, y and z codes that follow the above rules. the code combinations listed below have been fully verified. in addition to the following codes, the tpc codes may be shortened with zero padding techniques. contact aha application engineering for details. table 4: supported codes with recommended feedback values note: the feedback values listed in table 4 are recommended starting values. depending on the target bit error rate, the user may wish to adjust the feedback values slightly for more optimal performance. the aha4501 windows evaluation software can be used to fine tune the feedback for any selected configuration. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x02 oecc xfbck[2] ycode[2:0] zcode[2:0] 111 110 101 100 (64,57) (32,26) (16,11) (8,4) -- extended hamming codes * 011 010 001 (16,15) (8,7) (4,3) -- parity only codes - even parity * 000 no code * valid only in zcode[2:0] block configuration (n 1 ,k 1 )x(n 2 ,k 2 )x(n 3 ,k 3 ) block size (bits) data size (bits) code rate feedback (4 iterations) feedback (32 iterations) (64,57)x(64,57) 4096 3249 0.793 1/2,1/2 7/16,7/16 (32,26)x(32,26)x(4,3) 4096 2028 0.495 3/8,3/8,11/16 5/16,5/16,9/16 (16,11)x(16,11)x(16,11) 4096 1331 0.325 7/16,7/16,7/16 3/8,3/8,3/8 (32,26)x(16,11)x(8,4) 4096 1144 0.278 3/8,3/8,7/16 3/8,3/8,3/8 (64,57)x(32,26) 2048 1482 0.724 1/2,9/16 7/16,1/2 (32,26)x(16,11)x(4,3) 2048 858 0.419 3/8,7/16,11/16 5/16,3/8,9/16 (64,57)x(8,4)x(4,3) 2048 684 0.334 3/8,7/16,11/16 5/16,3/8,9/16 (32,26)x(32,26) 1024 676 0.660 1/2,1/2 7/16,7/16 (16,11)x(16,11)x(4,3) 1024 363 0.354 3/8,3/8,11/16 5/16,5/16,9/16 (32,26)x(16,11) 512 286 0.559 7/16,1/2 3/8,7/16 (16,11)x(16,11) 256 121 0.473 1/2,1/2 7/16,7/16
ps4501-1100 page 15 of 36 advanced hardware architectures, inc. 3.4 feedback, address 0x03 - read/write this register is initialized to 0x24 after hard reset, unchanged after soft reset. xfeedback[1:0] - feedback multiplier for x axis iteration. used only when decoding. yfeedback[2:0] - feedback multiplier for y axis iteration. used only when decoding. zfeedback[2:0] - feedback multiplier for z axis iteration. used only when decoding 3d codes. each feedback value is defined as follows: 000 - multiply feedback by 1/4 001 - multiply feedback by 5/16 010 - multiply feedback by 3/8 011 - multiply feedback by 7/16 100 - multiply feedback by 1/2 101 - multiply feedback by 9/16 110 - multiply feedback by 5/8 111 - multiply feedback by 11/16 refer to the section 2.3 decoding for a functional description of the feedback values. 3.5 quantization, address 0x04 - read/write this register is initialized to 0x0c after hard reset, unchanged after soft reset. res - reserved bits. must be written to 00. qshift[1:0] - quantization shift. used only when decoding; must be set to ? 00 ? when encoding. the input data can be shifted bitwise left inside the device before decoding begins. this is useful with smaller input quantization sizes. see section 2.1 data input for details about how to set this value. defined as follows: 00 - no shift 01 - shift input data left 1 (multiply by 2) 10 - shift input data left 2 (multiply by 4) 11 - shift input data left 3 (multiply by 8) qsize[1:0] - quantization size for soft input data. used only when decoding. specifies the number of bits of data for each soft input value. soft input data must always be driven on idata[qsize-1:0]. defined as follows: 00 - 1 bit, 2 bits 01 - 3 bits 10 - 4 bits 11 - 5 bits *see note 1 for 6 bit address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x03 xfeedback[1:0] yfeedback[2:0] zfeedback[2:0] address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x04 res qshift[1:0] qsize[1:0] qmode[1:0]
page 16 of 36 ps4501-1100 advanced hardware architectures, inc. notes: 1) 6 bit quantization is supported when qmode[1:0] = ?00?. since the data is in 2?s complement notation, the data on idata[5:0] is transferred directly to the oa sram. the value of qsize[1:0] is ignored when qmode[1:0]= ?00?. 2) 1 bit quantization (hard decision input) is supported by setting qsize[1:0] = ?00? and qmode[1:0] = ?01?. it is recommended that qshift[1:0] be set to ?11? for hard decision input data. the hard decision input is connected to idata[1]. idata[0] must be tied high. qmode[1:0] - quantization mode for soft input data. used only when decoding; must be set to ? 00 ? for encoding. when set to ? 00 ? , input data is assumed to be in signed 2's complement notation (mid-tread). when set to ? 01 ? , data is assumed to be mid-riser sign/magnitude notation. when set to ? 10 ? , data is assumed to be mid-riser unsigned. the confidence mapping for each mode is shown on the next page with four bit quantization. 3.6 corrections, address 0x05 - read this register is initialized to 0x00 after hard reset, unchanged after soft reset. corrections[7:0] - the eight least significant bits of the number of hard decision corrections made over the entire number of iterations executed on one block. the upper two most significant bits are accessed via the status register. this value is updated each time the compl interrupt bit is set. this value contains the count of the number of bits corrected between the input data (assuming hard decision decoding), and the output data. if the count overflows, the cflow bit is set, and the value of the count is invalid. invalid when encoding. 3.7 synchronization, address 0x05 - write this register is initialized to 0x00 after hard reset, unchanged after soft reset. sync mark length[3:0] - when decoding, the module can automatically remove sync marks from the incoming data stream. the number of bits to be discarded is 4 times the value of the sync mark length register. this allows sync marks to be from 4 to 60 bits in length. a value of zero results in no discarded bits. sync mark frequency[3:0] - the number of blocks between synchronization marks. when encoding, the osync signal asserts with the first bit of each x output blocks, where x is the value of sync mark frequency[3:0] in the sync register. when decoding, the isync is checked at the first bit of each x input blocks, where x is the value of sync mark frequency[3:0] in the sync register. if the isync signal is not asserted, the sync mark mismatch interrupt bit is set. a value of 1 indicates that the signals are asserted/checked at the start of every block. a value of 0 indicates every 32 blocks. see section 2.6 synchronization for more information. qmode[1:0] input data type hard decision 0 confidence range no confidence hard decision 1 confidence range max . . . min min . . . max 00 2 ? s complement 1000 . . . 1111 0000 0001 . . . 0111 01 sign/magnitude 0111 . . . 0000 n/a 1000 . . . 1111 10 unsigned 0000 . . . 0111 n/a 1000 . . . 1111 address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x05 corrections[7:0] address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x05 sync mark length [3:0] sync mark frequency[3:0]
ps4501-1100 page 17 of 36 advanced hardware architectures, inc. 3.8 status, address 0x06 - read only this register is initialized to 0x00 after hard reset, unchanged after soft reset. note : this register must not be written. niter[4:0] - number of iterations. the actual number of iterations performed in the last block decoded. this value is updated each time the compl interrupt bit is set. note that if the stiter bit is cleared, this value will always be equal to the programmed iter[4:0] value. the internal iteration value is incremented after a y-axis iteration is completed for 2d codes or after a z-axis iteration is completed for 3d codes. if the stiter bit is set, the iterations may finish after an axis iteration rather than a full iteration. in this case, the niter[4:0] value will be the number of full iterations completed. cflow - correction overflow. set if the corrections[9:0] count exceeded the value of 1024 corrections. when set, the corrections[9:0] count value is invalid. correct[9:8] - the two most significant bits of the number of hard decision corrections made over the entire set of iterations. this value is updated each time the compl interrupt bit is set. invalid when encoding. 3.9 control/interrupt, address 0x07 - read/write this register is initialized to 0x00 after hard reset. the interrupt bits [2:0] are reset, but all other register contents are unchanged after soft reset. note: all interrupts and bits 0, 1, 2 are cleared when this register is read. decode (r/w) - when set, the module performs decoding on the input data. the decode bit must not be set with the encode bit. if both bits are cleared, the module is idle and does not accept input data. the sreset bit should be written with or after clearing the decode bit to ensure proper operation. the decode bit should not be set within 5 clocks of sreset. encode (r/w) - when set, the module performs encoding on the input data. the output data is a serial bit stream of both data and ecc code bits. the encode bit must not be set with the decode bit. if both bits are cleared, the module is idle, and does not accept input data. the sreset bit should be written with or after clearing the encode bit to ensure proper operation. the encode bit should not be set within 5 clocks of sreset. corincm (r/w) - correction incomplete mask. when cleared, the mintn_intr interrupt signal is asserted when the corinc interrupt bit is asserted. when set, the interrupt signal is not asserted with corinc. smmism (r/w) - sync mark mismatch mask. when cleared, the mintn_intr interrupt signal is asserted when the smmis interrupt bit is asserted. when set, the interrupt signal is not asserted with smmis. complm (r/w) - block decode complete mask. when cleared, the mintn_intr interrupt signal is asserted when the compl interrupt bit is asserted. when set, the interrupt signal is not asserted with compl. address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0x06 niter[4:0] cflow correct[9:8] rd/wr bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 read decode encode corincm smmism complm corinc smmis compl write sreset resync dump
page 18 of 36 ps4501-1100 advanced hardware architectures, inc. corinc (r) - correction incomplete. the nature of the algorithm allows the module to determine if another iteration would be useful. when the module has reached the maximum number of iterations programmed in iter[4:0], a check is done to determine if another iteration would be useful. if another iteration would be useful, then the data in the block may or may not be correct, and the corinc interrupt bit is set. note that this bit is pessimistic, meaning that it may be asserted when errorless data is output from the device when the last correction happens on the last iteration. this is especially true when the value of iter[4:0] is 2 or less. therefore, it must not be used to discard a block of data if set. its use is more valuable in verifying that a correct synchronization of data has occurred, or that synchronization has been lost. this bit is never set when encoding. sreset (w) - soft reset. writing a 1 to this bit causes a reset of the entire data path. the input and output ports immediately stop handshaking data. the control/interrupt register bits [2:0] are reset, but all other register contents are unaffected by sreset. note that all data internal to the module is lost. sreset should not be issued at the same time as either decode or encode. smmis (r) -sync mark mismatch. after the first block of data has been input to the device, each x block is checked for assertion of the isync signal with the first bit of the block, where x is the value of sync mark frequency[3:0] in the sync register. if the isync signal is not asserted when the module is at the start of a new block, the smmis bit is set. note, however, that when this condition occurs, the module assumes the isync signal is incorrect, and does not set the write pointers to the beginning of the block. if this is necessary, the microprocessor must issue a resynchronize command by setting the resync bit of the control register. this bit will never be set when encoding. resync (w) - resynchronize. when decoding, if the microprocessor has determined that synchronization has been lost in the data stream, it can issue a resync by writing a one to this bit. this will cause the module to stop reading input data bits, discard all data read in the current input block, and wait for an isync signal. note that the block that is being decoded when a resync is issued will be output to the data port. this bit must not be set when encoding. compl (r) - block decode complete set at the completion of each block encoding or decoding cycle, indicating that the block is ready to be output. when decoding, the value of niter[4:0], and the corrections[9:0] count value in the correct and status registers are updated each time the compl bit is set. the corinc bit will also be set with compl if the incomplete condition was detected. dump (w) -dump current block. when decoding, writing a 1 to this bit will cause the module to stop iterations on the current block and send it to the output data port. the dump occurs upon completion of the axis iteration following the current axis iteration. the worst case delay is two axis iterations (which is equal to one full iteration for 2d codes). decoding then begins on the next (already loaded) data block, and another block can begin loading. 3.10 reserved, address 0x08 - reserved this register is for production test purposes only.
ps4501-1100 page 19 of 36 advanced hardware architectures, inc. 4.0 performance curves the following figures show a comparison between the (64,57)x(64,57) tpc implementation which has a code rate of 0.793, and two reed-solomon/viterbi implementations with code rates of 0.806 and 0.790. the modulation is phase shift keying (psk), and the channel model is additive white gaussian noise (awgn). note that the tpc implementation consistently outperforms the rs/viterbi implementations at 2 iterations. additional iterations increase tpc performance. figure 12: turbo product code vs. reed-solomon/viterbi performance comparison figure 13 shows the performance of the three 4k block codes in the same channel with 32 iterations. figure 13: comparison of tpc code types figure 14 shows the e b /n o required to achieve a bit error rate (ber) of 10 -5 . using the (64,57)x(64,57) block code in an awgn channel. this figure shows the correction performance trade-offs between input quantization bits and iterations (data rate). optimum performance occurs with 32 iterations and 6 input quantization bits, however, excellent performance can be achieved with only 3 input quantization bits or only 3 iterations. 12345678910 eb/no (db) 10 ?8 10 ?7 10 ?6 10 ?5 10 ?4 10 ?3 10 ?2 10 ?1 10 0 bit error rate, p(e) turbo product code vs. reed?solomon/viterbi (64,57) x (64,57) hamming product code, rate = 0.793 uncoded psk, rate=1 rs/viterbi, rate=0.806 rs/viterbi, rate=0.790 tpc, 1 iteration 2 iterations 3 iterations 4 iterations 6 iterations 32 iterations shannon capacity turbo product code performance aha4501 evm, 4096 bit blocks 1.e-11 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 012345678910 eb/no (db) bit error rate p(e) uncoded psk cha nnel (64,57)x(64,57), r=.793 (32,26)x(32,26)x(4,3), r=.495 "(16,11)x(16,11)x(16,11), r=.325
page 20 of 36 ps4501-1100 advanced hardware architectures, inc. figure 14: performance curve of e b /n o for ber of 10 -5 5.0 signal descriptions this section contains descriptions for all the pins. each signal has a type code associated with it. the type codes are described in the following table. 5.1 system control type code description i input only pin o output only pin i/o input/output pin s synchronous signal a asynchronous signal signal type description clk i system clock. 50 mhz maximum frequency. resetn i a power on reset. active low reset signal. resetn should be a minimum of 4 clock periods. when resetn is asserted, all registers are reset as defined in section 3.0 internal register programming , all control signals are deasserted, and the data path is cleared. tri_state i tristate enable. when this pin is asserted high, the i/o and output signal drivers are tristated. tied low for normal operation. testmode i testmode enable. tied low for normal operation. 32 16 12 8 6 5 4 3 2 1 6 5 4 3 2 1 3 3.25 3.5 3.75 4 4.25 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 6.75 e b /n 0 (db) for ber = 10 - 5 iterations soft input bits 6-7 5-6 4.5-5 4-4.5 3.75-4 3.5-3.75 3.25-3.5 3-3.25 e b /n 0
ps4501-1100 page 21 of 36 advanced hardware architectures, inc. 5.2 microprocessor interface 5.3 input interface 5.4 output interface signal type description mdata[7:0] i/o a processor data. data for all microprocessor reads and writes of registers within the aha4501 transfers across this bus. ma[2:0] i a processor address bus. used to address internal registers within the aha4501. mcsn i a processor chip select. selects the aha4501 as the source or destination of the current microprocessor bus cycle. mcsn needs to be active for a minimum of one clock cycle to start a microprocessor access. mwrn_rwn i a processor read/write select. when procmode is deasserted, this is the active low write enable signal. when procmode is asserted, this is the active low read/write select signal. mrdy_dtackn o a processor ready/data transfer acknowledge. when procmode is deasserted, this is an active high ready signal. when procmode is asserted, this signal is an active low data transfer acknowledge. mrdn_dsn i a processor read enable/data strobe. when procmode is deasserted, this is the active low read enable signal. when procmode is asserted, this is the active low data strobe signal. mintn_intr o a processor interrupt. when procmode is deasserted, this signal is active high. when procmode is asserted, this signal is active low. male i a processor address latch enable. when procmode is not asserted and muxmode is asserted, this signal is the active high address latch enable. otherwise, this pin is not used and must be tied low. procmode i a processor mode. intel ? mode when deasserted, motorola ? mode when asserted. muxmode i a muxed processor mode. deassert for non-muxed address and data bus mode, assert for muxed address and data bus mode. signal type description idata[7:0] i s data input bus. irdy i s input data ready. data is registered into the aha4501 on the rising edge of clock when irdy and iacpt are asserted. iacpt o s input data accept. data is registered into the aha4501 on the rising edge of clock when irdy and iacpt are asserted. isync i s input synchronize. asserted with idata for the first bit of data after the detection of a sync mark in the data stream. isync is ignored when encoding. signal type description odata[7:0] o s data output bus. ordy o s output data ready. data is registered out of the aha4501 on the rising edge of clock when ordy and oacpt are asserted. oacpt i s output data accept. data is registered out of the aha4501 on the rising edge of clock when ordy and oacpt are asserted. osync o s output synchronize. asserted with odata for the first bit in every x blocks, as programmed in the sync mark frequency[3:0] section of the sync register.
page 22 of 36 ps4501-1100 advanced hardware architectures, inc. 6.0 pinout table 5: pin designation nc - not connected internally. pin signal pin signal pin signal 1 male 41 gnd 81 idata[6] 2 mcsn 42 vdd 82 idata[7] 3 gnd 43 odata[1] 83 nc 4 ma[0] 44 odata[2] 84 vdd 5 vdd 45 odata[3] 85 nc 6 gnd 46 vdd 86 gnd 7 ma[1] 47 gnd 87 nc 8 ma[2] 48 odata[4] 88 nc 9 vdd 49 odata[5] 89 nc 10 tied gnd 50 vdd 90 vdd 11 gnd 51 gnd 91 gnd 12 mintn_intr 52 nc 92 muxmode 13 mrdy_dtackn 53 odata[6] 93 testmode 14 nc 54 odata[7] 94 resetn 15 mdata[7] 55 vdd 95 mrdn_dsn 16 mdata[6] 56 gnd 96 mwrn_rwn 17 vdd 57 ordy 97 gnd 18 gnd 58 osync 98 tri_state 19 mdata[5] 59 iacpt 99 vdd 20 mdata[4] 60 nc 100 procmode 21 mdata[3] 61 nc 22 mdata[2] 62 gnd 23 vdd 63 gnd 24 gnd 64 vdd 25 mdata[1] 65 vdd 26 mdata[0] 66 clk 27 nc 67 isync 28 nc 68 irdy 29 nc 69 oacpt 30 nc 70 idata[0] 31 vdd 71 idata[1] 32 gnd 72 gnd 33 nc 73 idata[2] 34 nc 74 gnd 35 nc 75 vdd 36 vdd 76 vdd 37 gnd 77 idata[3] 38 nc 78 idata[4] 39 nc 79 idata[5] 40 odata[0] 80 gnd
ps4501-1100 page 23 of 36 advanced hardware architectures, inc. figure 15: pinout ? 100 mqfp aha4501-050 pqc 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 31 tm 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 male mcsn gnd ma[0] vdd gnd ma[1] ma[2] vdd tied gnd gnd mintn_intr mrdy_dtackn nc mdata[7] mdata[6] vdd gnd mdata[5] mdata[4] mdata[3] mdata[2] vdd gnd mdata[1] mdata[0] nc nc nc nc gnd idata[5] idata[4] idata[3] vdd vdd gnd idata[2] gnd idata[1] idata[0] oacpt irdy isync clk vdd vdd gnd gnd nc nc iacpt osync ordy gnd vdd odata[7] odata[6] nc gnd vdd odata[5] odata[4] gnd vdd odata[3] odata[2] odata[1] vdd gnd odata[0] nc nc gnd vdd nc nc nc gnd vdd idata[6] idata[7] nc vdd nc gnd nc nc nc vdd gnd muxmode testmode resetn mrdn_dsn mwrn_rwn gnd tri_state vdd procmode
page 24 of 36 ps4501-1100 advanced hardware architectures, inc. 7.0 electrical specifications 7.1 absolute maximum ratings absolute maximum voltage ratings are for voltage excursions which are transitory in nature. 7.2 recommended operating conditions 7.2.1 dc specifications figure 16: current vs. data rate (typ) symbol parameter min max units v dd power supply voltage 4.6 volts v pin voltage applied to any pin -0.5 4.6 volts symbol parameter min max units v dd power supply voltage 3.0 3.6 volts t a operating temperature 0 70 c symbol parameter conditions min max units v il input low voltage ? 0.3 0.8 volts v ih input high voltage 2.0 v dd ? 0.3 volts v ol output low voltage 4ma output loads 0.4 volts v oh output high voltage 4ma output loads 2.4 volts i il input low current v in = 0 volts -5 amps i ih input high current v in = v dd vo l t s 5 amps i dd active i dd current 50 mhz clock, decoding at maximum data rate, v dd =3.3v, no loads 250 mamps i dd supply current (static) 1.0 mamps i dd standby current chip idle, 50 mhz clock, v dd =3.3v, no loads 20 mamps i ol output low current 4 mamps i oh output high current 4 mamps 10 50 50 100 150 200 250 clock (mhz) current (ma) 20 30 40 0
ps4501-1100 page 25 of 36 advanced hardware architectures, inc. 7.2.2 test conditions note: the timing diagrams for these signals assume a capacitive load of 20pf. the specified signal timings must be derated by the factor shown in figure 17 when operating at loads other than 20pf. figure 17: signal timing vs. output load *production test conditions 7.2.3 pin capacitance notes: not tested in production. parameter value ac timing reference 1.4 v 10 50 0.9 1.0 1.1 1.2 1.3 load capacitance (pf) multiplication factor 20 30 40 load capacitance multiplication factor 10 pf 0.92 20 pf 1.00 30 pf 1.08 40 pf 1.16 50 pf* 1.25 symbol parameter max units c in input capacitance 10 pf c out output self load capacitance 10 pf c io i/o self load capacitance 10 pf
page 26 of 36 ps4501-1100 advanced hardware architectures, inc. 8.0 timing specifications figure 18: data input timing note: for the first block after reset, the input data is discarded until the isync signal is asserted (decoding only). table 6: data input timing requirements figure 19: data output timing table 7: data output timing requirements number parameter min max units notes 1 irdy, isync, idata setup to clk rising edge 5 ns 2 iacpt delay from clk rising edge 9 ns 3 irdy, isync, idata hold from clk rising edge 2 ns 4 iacpt hold from clk rising edge 2 ns number parameter min max units notes 1 oacpt setup to clk rising edge 5 ns 2 ordy, osync, odata delay from clk rising edge 9ns 3 oacpt hold from clk rising edge 2 ns 4 ordy, osync, odata hold from clk rising edge 2 ns data 1 clk irdy (in) iacpt (out) isync (in) idata[7:0] (in) 4 discard data see note data 0 2 1 3 clk ordy (out) oacpt (in) osync (out) odata[7:0] (out) 4 data 1 2 1 3 data 0 data 2 2 2
ps4501-1100 page 27 of 36 advanced hardware architectures, inc. figure 20: microprocessor interface timing (write); procmode=0, muxmode=0 table 8: microprocessor interface timing requirements - write notes: 1) the microprocessor interface can be asynchronous to clk. the above timings indicate the required setup and hold to allow for fastest microprocessor accesses. 2) write cycle begins when both mcsn and mwrn_rwn are low and meet setup to rising edge of clk. 3) mcsn may be held low continuously for back to back accesses. 4) neither mrdn_dsn nor mwrn_rwn may pulse high or low for less than one clock period. 5) tcp = clock period. (ns) 6) asynchronous operation only number parameter min max units notes 1 mcsn, mwrn_rwn setup to clk rising edge 5 ns 1,2,3,4 2 mwrn_rwn low to mdata[7:0] valid 1 tcp ? 3ns ns 5 3 clk rising edge to mrdy_dtackn high 15 ns 4 mcsn high to mrdy_dtackn tristate 12 ns 5 mcsn low to mrdy_dtackn active 12 ns 6 mwrn_rwn low to mrdy_dtackn low 15 ns 7 mcsn low setup to mwrn_rwn low 2 ns 6 clk ma[2:0] (in) mdata[7:0] (in) mcsn (in) mwrn_rwn (in) 1 data address mrdy_dtackn (out) 1 2 1 4 5 6 3 7
page 28 of 36 ps4501-1100 advanced hardware architectures, inc. figure 21: microprocessor interface timing (read); procmode=0, muxmode=0 table 9: microprocessor interface timing requirements - read; procmode=0, muxmode=0 notes: 1) the microprocessor interface can be asynchronous to clk. the above timings indicate the required setup and hold to allow for fastest microprocessor accesses. 2) write cycle begins when both mcsn and mrdn_dsn are low and meet setup to rising edge of clk. 3) mcsn may be held low continuously for back to back accesses. 4) neither mrdn_dsn nor mwrn_rwn may pulse high or low for less than one clk period. 5) tcp = clock period. (ns) 6) asynchronous operation only. number parameter min max units notes 1 mcsn/mrdn_dsn setup to clk rising edge 5 ns 1,2,3,4 2 clk rising edge to mdata[7:0] valid 11 ns 3 mcsn low to mrdy_dtackn active 12 ns 4 mrdn_dsn low to mrdy_dtackn low 15 ns 5 ma[2:0] valid from mrdn_dsn low 1 tcp ? 3ns ns 5 6 mrdn_dsn high to mdata[7:0] tristate 2 12 ns 7 ma[2:0] hold from mrdn_dsn 0 ns 8 mcsn high to mrdy_dtackn tristate 12 ns 9 clk rising edge to mrdy_dtackn high 3 15 ns 10 mcsn low setup to mrdn_dsn low 2 ns 6 clk mcsn (in) mrdn_dsn (in) ma[2:0] (in) mdata[7:0] (out) 1 data mrdy_dtackn (out) 1 5 2 3 8 1 address 7 6 9 4 10
ps4501-1100 page 29 of 36 advanced hardware architectures, inc. figure 22: microprocessor interface timing (write); procmode=0, muxmode=1 table 10: microprocessor interface timing requirements - write; procmode=0, muxmode=1 notes: 1) the microprocessor interface can be asynchronous to clk. the above timings indicate the required setup and hold to allow for fastest microprocessor accesses. 2) write cycle begins when both mcsn and mwrn_rwn are low and meet setup to rising edge of clk. 3) mcsn may be held low continuously for back to back accesses. 4) neither mrdn_dsn nor mwrn_rwn may pulse high or low for less than one clock period. 5) asynchronous operation only. number parameter min max units notes 1 address hold from male falling edge 10 ns 2 address setup to male falling edge 7 ns 3 mcsn/mwrn_rwn setup to clk rising edge 10 ns 1,2,3,4 4 male hold from mwrn_rwn rising edge 0 ns 5 male setup to mwrn_rwn falling edge 10 ns 6 write data setup to mwrn_rwn falling edge 0 ns 7 mdata[7:0] and csn hold from mwrn_rwn rising edge 0ns 8 mwrn_rwn low width 2 clocks 9 male high width 10 ns 10 mcsn low to mrdy_dtackn active 12 ns 11 clk rising edge to mrdy_dtackn high 15 ns 12 mcsn high to mrdy_dtackn tristate 12 ns 13 mcsn low setup to mwrn_rwn low 2 ns clk male (in) mdata[7:0] (in) mcsn (in) mwrn_rwn (in) data mrdy_dtackn (out) 3 2 6 5 11 addr 1 3 3 10 8 12 7 4 9 13
page 30 of 36 ps4501-1100 advanced hardware architectures, inc. figure 23: microprocessor interface timing (read); procmode=0, muxmode=1 table 11: microprocessor interface timing requirements - read; procmode=0, muxmode=1 notes: 1) the microprocessor interface can be asynchronous to clk. the above timings indicate the required setup and hold to allow for fastest microprocessor accesses. 2) write cycle begins when both csn and mrdn_dsn are low and meet setup to rising edge of clk. 3) csn may be held low continuously for back to back accesses. 4) neither mrdn_dsn nor mwrn_rwn may pulse high or low for less than one clk period. 5) tcp = clock period. (ns) 6) asynchronous operation only. number parameter min max units notes 1 mcsn/mrdn_dsn setup to clk rising edge 10 ns 1,2,3,4 2 male hold from mrdn_dsn rising edge 0 ns 3 male setup to mrdn_dsn falling edge 10 ns 4 address setup to male falling edge 7 ns 5 address hold from male falling edge 10 ns 6 mcsn hold from mrdn_dsn rising edge 0 ns 7 mrdn_dsn low width 2 clocks 5 8 mrdn_dsn falling edge to mdata[7:0] valid 2 tcp+11 ns ns 5 9 mrdn_dsn high to mdata[7:0] tristate 2 12 ns 10 rising edge of clk to mdata[7:0] valid 11 ns 11 male high width 10 ns 12 mcsn low to mrdy_dtackn active 12 ns 13 mrdn_dsn low to mrdy_dtackn low 15 ns 14 mcsn high to mrdy_dtackn tristate 12 ns 15 clk rising edge to mrdy_dtackn high 3 15 ns 16 mcsn low setup to mrdn_dsn low 2 ns 6 clk male (in) mcsn (in) mrdn_dsn (in) mdata[7:0] (in/out) 1 data mrdy_dtackn (out) 1 4 14 3 2 9 10 13 addr 5 12 1 8 15 7 11 6 16
ps4501-1100 page 31 of 36 advanced hardware architectures, inc. figure 24: microprocessor interface timing (write); procmode=1, muxmode=0 table 12: microprocessor interface timing requirements - write; procmode=1, muxmode=0 notes: 1) the microprocessor interface can be asynchronous to clk. the above timings indicate the required setup and hold to allow for fastest microprocessor accesses. 2) write cycle begins when both mcsn and mwrn_rwn are low and meet setup to rising edge of clk. 3) mcsn may be held low continuously for back to back accesses. 4) neither mrdn_dsn nor mwrn_rwn may pulse high or low for less than one clock period. only required to be recognized on current clock edge. if less than this number, cycle will be recognized on the next clock. 5) tcp = clock period. (ns) 6) asynchronous operation only. number parameter min max units notes 1 mcsn, mrdn_dsn, mwrn_rwn setup to clk rising edge 5 ns 1,2,3,4 2 mrdn_dsn low to mdata[7:0] valid 1 tcp ? 3ns ns 5 3 mrdn_dsn low to ma[2:0] valid 1 tcp ? 3ns ns 5 4 mcsn low to mrdy_dtackn active 12 ns 5 mrdn_dsn low to mrdy_dtackn high 15 ns 6 clk rising edge to mrdy_dtackn low 15 ns 7 mcsn high to mrdy_dtackn tristate 0 ns 8 mcsn low setup to mrdn_dsn low 2 ns 6 clk mrdn_dsn (in) ma[2:0] (in) mcsn (in) mwrn_rwn (in) address mrdy_dtackn (out) 1 4 2 mdata[7:0] (in) data 1 3 5 6 7 1 8
page 32 of 36 ps4501-1100 advanced hardware architectures, inc. figure 25: microprocessor interface timing (read); procmode=1, muxmode=0 table 13: microprocessor interface timing requirements - read; procmode=1, muxmode=0 notes: 1) the microprocessor interface can be asynchronous to clk. the above timings indicate the required setup and hold to allow for fastest microprocessor accesses. 2) write cycle begins when both mcsn and mrdn_dsn are low and meet setup to rising edge of clk. 3) mcsn may be held low continuously for back to back accesses. 4) neither mrdn_dsn nor mwrn_rwn may pulse high or low for less than one clk period. 5) tcp = clock period. (ns) 6) asynchronous operation only. number parameter min max units notes 1 mcsn, mrdn_dsn, mwrn_rwn setup to clk rising edge 5 ns 1,2,3,4 2 mcsn low to mrdy_dtackn active 12 ns 3 mrdn_dsn low to mrdy_dtackn high 15 ns 4 address valid from mrdn_dsn low 1 tcp ? 3ns ns 5 5 clk rising edge to mdata[7:0] valid 11 ns 6 clk rising edge to mrdy_dtackn low 3 15 ns 7 mrdn_dsn high to mrdy_dtackn tristate 12 ns 8 mcsn low to mrdn_dsn low 2 ns 6 clk mrdn_dsn (in) mcsn (in) mwrn_rwn (in) mdata[7:0] (out) 1 mrdy_dtackn (out) 1 3 7 ma[2:0] (in) data 4 2 address 5 6 1 8
ps4501-1100 page 33 of 36 advanced hardware architectures, inc. figure 26: interrupt timing table 14: interrupt timing requirements figure 27: clock timing table 15: clock timing requirements notes: 1) not tested in production. figure 28: power on reset timing table 16: power on reset timing requirements notes: 1) resetn signal can be asynchronous to the clock signal. it is internally synchronized to the rising edge of clock. number parameter min max units notes 1 mintn_intr delay time 12 ns 2 mintn_intr hold time 2 ns number parameter min max units notes 1 clock rise time 2 ns 1 2 clock fall time 2 ns 1 3 clock high time 8 ns 4 clock low time 8 ns 5 clock period 20 ns number parameter min max units notes 1 resetn low pulsewidth 4 clocks 2 resetn setup to clock rise 6 ns 1 3 resetn hold time 3 ns 1 clk mintn_intr 1 2 (out) clk 1 34 5 2 2.0v 1.4v 0.8v clk resetn 2 3 1
page 34 of 36 ps4501-1100 advanced hardware architectures, inc. 9.0 packaging figure 29: aha4501 package specifications ? 100 mqfp table 17: pqfp (plastic quad flat pack) 14 20 mm package dimensions jedec outline mo-112 (all dimensions are in mm) symbol number of pin and specification dimension 100 rb min nom max (lca) 20 (lcb) 30 a3.1 a1 0.1 0.23 0.36 a2 2.57 2.71 2.87 d 23.65 23.9 24.15 d1 19.9 20 20.1 e 17.65 17.9 18.15 e1 13.9 14 14.1 l 0.73 0.88 1.03 p0.65 b 0.22 0.3 0.33 aha4501a-050 pqc tm d1 p d b e1 p e (lca) (lcb) 81 82 83 84 85 96 97 98 99 100 30 29 28 27 26 l a a2 a1
ps4501-1100 page 35 of 36 advanced hardware architectures, inc. 10.0 ordering information 10.1 available parts 10.2 part numbering device number: 4501 revision letter: a speed designation: 50 mhz package material codes: p plastic package type codes: qquad test specifications: c commercial 0 c to +70 c part number description aha4501-050 pqc aha4501 astro 36 mbits/sec turbo product code encoder/decoders , 3.3 v aha 4501 a 050 p q c manufacturer device number revision level speed designation package material package type test specification
page 36 of 36 ps4501-1100 advanced hardware architectures, inc. 11.0 related publications this product and the algorithm are covered under multiple applied patents. part number description pb4501 aha product brief ? aha4501 astro 36 mbits/sec turbo product code encoder/decoder pb4501evm aha product brief ? aha4501 tpc evm isa evaluation module pb4501evsw aha product brief ? aha4501 tpc windows evaluation software pb4540 aha product brief ? aha4540 astro oc-3 155 mbits/sec turbo product code encoder/decoder pbgalaxy aha product brief ? galaxy core generator turbo product code decoder cores pbgalaxy_evsw aha product brief ? aha galaxy tpc windows evaluation software pbgalaxy_stk aha product brief ? aha galaxy simulation tool kit ps4540 aha product specification ? aha4540 astro oc-3 155 mbits/sec turbo product code encoder/decoder antpc01 aha application note ? primer: turbo product codes antpc02 aha application note ? use and performance of shortened codes with the aha4501 turbo product code encoder/decoder antpc03 aha application note ? use and performance of the aha4501 turbo product code encoder/decoder with quadrature amplitude modulation (qam) antpc04 aha application note ? use and performance of the aha4501 turbo product code encoder/decoder with differential phase shift keying (dpsk) antpc05 aha application note ? aha4501 turbo product code encoder/decoder designer ? s guide antpc06 aha application note ? aha4501 turbo product code encoder/decoder frequently asked questions (faq) antpc07 aha application note ? turbo product codes for lmds antpc08 aha application note ? using multiple aha4501 devices in parallel for higher data rates tpceval aha evaluation software ? turbo product codes - windows evaluation software

▲Up To Search▲

Price & Availability of AHA4501-050PQC

	To Download AHA4501-050PQC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .